In IC packaging there is a need to provide semiconductor dies in a side-by-side configuration within a package and interconnect them. The package may be, for example, a lead frame package.
In one configuration, semiconductor dies are packaged with the active side of each die facing away from the package base. Interconnection between dies is achieved by wire bonding. However, design rules for assembly interconnection may be limited by dimensions of the wire diameter and wire-bonding capillary tool, requiring bonding pads that are large enough and spaced sufficiently far apart to accommodate the dimensions. Thus the number of interconnects is limited by the size of the interconnects. In addition, lead inductance in the die-to-die wire bond may limit performance of the packaged device. Furthermore, gold wire is a conventional choice for wire bonding, increasing significantly the net cost of the package.
In another configuration, flip-chip solderball packaging, the active device region of the die is on the surface facing the package mounting substrate, e.g., downward. In this configuration, interconnection density between adjacent dies is also limited by contact pad size requirements.
U.S. Pat. No. 5,225,633 discloses interconnecting two semiconductor dies in a side-by-side configuration using bridge elements. Each bridge element comprises a rigid silicon die supporting overhanging conducting beam leads. The bridge is placed in a space between two semiconductor dies, and the extent of overhang of each beam lead and adjacent positioning are selected to provide proper mating with bonding pads positioned on each of the semiconductor dies to be interconnected. However, no method of forming the beam leads or disposing them on the silicon bridge is disclosed. Moreover, handling and assembling beam leads may be difficult, and the bridge occupies space between the two dies. Furthermore, as gold is a preferred interconnect metal, there is an impact on the material cost of the assembled package.
There is a need, therefore, for a packaging interconnect system between adjacent semiconductor dies that simplifies the assembly process, reduces the cost of interconnect materials, and enables interconnection between chips with a finer pitch than is conventionally permissible with wire bonding and equivalent beam lead interconnections.